![equalization for high-speed serdes: system-level comparison of analog and digital techniques equalization for high-speed serdes: system-level comparison of analog and digital techniques](https://www.analog.com/-/media/analog/en/landing-pages/technical-articles/integrated-hardened-dsp-on-dac-adc-ics-improves-wideband-multichannel-systems/353723-fig-11.jpg)
- Equalization for high speed serdes: system level comparison of analog and digital techniques how to#
- Equalization for high speed serdes: system level comparison of analog and digital techniques software#
TI also supports a complete system-level mockup of a multievaluation module prototype from a single PC. Great examples of support boards are the TSW1400EVM for LVDS/CMOS or the TSW14J56EVM for supporting JESD204B serializer-deserializer (SerDes) protocol devices, as shown in Figure 3.įigure 3: TI’s TSW14J56EVM for JESD204B data capture or pattern generation
Equalization for high speed serdes: system level comparison of analog and digital techniques software#
If your evaluation needs become complex, you can use Python, Matlab, Labview or C++ software to directly communicate with the device through the device evaluation board, the capture card solution and the test-bench equipment. See Figure 2.įigure 2: TI’s data-capture and pattern-generation hardware and softwareĪs systems become more complicated, you may need to evaluate across a broader range of use cases. Using the evaluation board user’s guide for your high-speed data converter, it’s possible to get most boards up and running in less than 10 minutes. Our data-capture and pattern-generation tools support CMOS, LVDS and JESD204, and come with the software needed to operate them. Once you have validated the performance, you can use the schematics and layout of the more complete evaluation board as a reference design for that portion of the subsystem. What TI has done in most cases is provide onboard power and clocking so that you can begin running the board with minimal test bench equipment and more realistic power supplies and signal sources, such as the setup shown in Figure 1. Once you have obtained the equipment necessary for running the typical evaluation board, component evaluation usually occurs with very idealistic supplies and signal sources.
![equalization for high-speed serdes: system-level comparison of analog and digital techniques equalization for high-speed serdes: system-level comparison of analog and digital techniques](https://www.signalintegrityjournal.com/ext/resources/article-images-2019/Feedforward-Equalizer-Location-Study-for-High-Speed-Serial-Systems/Fig-1.jpg)
In this article, I’ll take a closer look at each of these challenges.īefore starting a new hardware design, engineers often evaluate the most important chips on their own test bench.
Equalization for high speed serdes: system level comparison of analog and digital techniques how to#
Issues might include connecting with your field-programmable gate array (FPGA), being confident that your first design pass will work or determining how to best model the system before building it. Whether you’re designing an aerospace and defense system, test and measurement equipment or automotive lidar analog front end (AFE), hardware designers using modern high-speed data converters face tough challenges with high-frequency inputs, outputs, clock rates and digital interface.